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SP5659
2*7GHz I2C Bus Low Phase Noise Synthesiser Preliminary Information
DS4296 ISSUE 2.2 May 2002
The SP5659 is a single chip frequency synthesiser designed for tuning systems up to 2*7GHz. The RF preamplifier drives a divide-by two prescaler which can be disabled for applications up to 2GHz, allowing direct interfacing with the programmable divider, resulting in a step size equal to the comparison frequency. For applications up to 2*7GHz the divide-by two is enabled to give a step size of twice the comparison frequency. The comparison frequency is obtained either from an onchip crystal controlled oscillator or from an external source. The oscillator frequency FREF or the comparison frequency FCOMP may be switched to the REF/COMP output; this feature is ideally suited to providing the reference frequency for a second synthesiser such as in a double conversion tuner (see Fig. 5). The synthesiser is controlled via an I 2C bus and responds to one of four programmable addresses which are selected by applying a specific voltage to the Address input. This feature enables two or more synthesisers to be used in a system. The SP5659 contains four switching ports, P0-P3 and a 5-level ADC, the output of which can be read via the I 2C bus. The SP5659 also contains a varactor line disable and charge pump disable facility.
Ordering Information
SP5659/KG/MP1S (Tubes) SP5659/KG/MP1T (Tape and reel) (16-lead miniature Plastic Package)
CHARGE PUMP CRYSTAL REF/COMP ADDRESS SDA SCL PORT P3 PORT P2
1 2 3 4 5 6 7 8
16 15 14 13
DRIVE VEE RF INPUT RF INPUT VCC ADC PORT P0 PORT P1
SP5659
12 11 10 9
MP16
Figure 1 - Pin connections - top view
Features * Complete 2*7GHz Single Chip System * * * * * * * Optimised for Low Phase Noise Selectable 42 prescaler Selectable Reference Division Ratio Selectable Reference/Comparison Frequency Output Selectable Charge Pump Current Varactor Drive Amplifier Disable 5-Level ADC
* * *
Variable I2C BUS Address for Multi-tuner Applications ESD Protection: 4kV, Mil-Std-883C, Method 3015 (1) Pin Compatible with SP5658
(1) Normal ESD handling precautions should be observed.
Applications * Satellite TV * High IF Cable Tuning Systems Thermal Data
uJC = 41C/W uJA = 111C/W
SP5659
Preliminary Information
ELECTRICAL CHARACTERISTICS
TAMB = -20C to +80C, VCC = +4*5V to +5*5V, reference frequency = 4MHz. These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Value Characteristic Supply current, ICC RF input voltage Pin 12 13,14 50 Min. 68 58 Max. 85 73 300 Units mA mA Conditions VCC = 5V, PE = 1 (note 1) VCC = 5V, PE = 0
mVrms 300MHz to 2*7GHz, PE = 1 (prescaler enabled) see Fig. 4b mVrms 100MHz, PE = 1 (prescaler enabled) see Fig. 4b mVrms 100MHz to 2*0GHz, PE = 0 (prescaler disabled) see Fig. 4b pF See Fig. 10 See Fig. 10
RF input impedance RF input capacitance SDA, SCL Input high voltage Input low voltage Input high current Input low current Leakage current Input hysteresis SDA Output voltage Charge Pump Output current Output leakage current Drive output current Drive saturation voltage External reference input frequency External reference input amplitude Crystal frequency Crystal oscillator drive level Recommended crystal series resistance Crystal oscillator negative resistance REF/COMP output voltage, enabled Comparison frequency Equivalent phase noise at phase detector RF division ratio Reference division ratio P0, P1, P2, P3 sink current P0, P1, P2, P3 leakage current ADC input voltage ADC input current Address input current high Address input current low
13,14 13,14 5, 6 5, 6 5, 6 5, 6 5, 6 5, 6 5 1 1 16 16 2 2 2 2 2 3 3 0
50 2 5*5 1*5 10 -10 10 0*8 0*4
V V A A A V V
Input voltage = VCC Input voltage = VEE VCC = VEE Sink current = 3mA
+- 3 1 2 200 4 35 10 400 350
+- 1 0 350 200 20 500 16 200
nA mA mV MHz mVp-p MHz mVp-p
Drive output disabled AC coupled sinewave AC coupled sinewave
Parallel resonant crystal (note 2) Includes temperature and process tolerances
mVp-p AC coupled, RE = 1, see note 3 2 MHz dBC/Hz See note 4 Prescaler disabled, see Table 1 Prescaler enabled, see Table 1 See Table 1 mA A A mA mA VPORT = 0*7V VPORT = 13*2V See Fig. 3 Table 5 VCC >VINPUT >VEE Input voltage = VCC Input voltage = VEE
- 142 240 480 7,8,9,10 11 11 4 4 10 10 6 10 1 - 0*5 131071 262142
NOTES 1. Maximum power consumption is 468mW with VCC = 5*5V and all ports off. 2. Resistance specified is maximum under all conditions including start up. 3. If the REF/COMP output is not used, it should be left open circuit or connected to VCC and disabled by setting RE to logic 0. 4. 6kHz loop bandwidth, phase comparator frequency 250kHZ. Figure measured at 1kHz offset DSB (within loop bandwidth).
2
Preliminary Information
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to VEE at 0V Parameter Pin Min. Supply voltage RF input voltage RF input DC offset Port voltage Total port current ADC input DC offset REF/COMP output DC offset Charge pump DC offset Drive DC offset Crystal oscillator DC offset Address DC offset SDA, SCL input voltage Storage temperature Junction temperature 12 13,14 13, 14 7-10 7-10 7-10 11 3 1 16 2 4 5, 6 -0*3 -0*3 -0*3 -0*3 -0*3 -0*3 -0*3 -55 -0*3 -0*3 -0*3 Value Max. 7 2*5 V CC +0*3 14 6 50 V CC +0*3 V CC +0*3 V CC +0*3 V CC +0*3 V CC +0*3 V CC +0*3 6 + 150 + 150 V V p-p V V V mA V V V V V V V C C Units
SP5659
Conditions
Port in off state Port in on state
3
PREAMP
13
PROGRAMMABLE DIVIDER 13-BIT COUNT 4-BIT COUNT FPD PHASE COMP
FCOMP REFERENCE DIVIDER (SEE TABLE 1)
REF/COMP
OSC
2
RF IN
14
42/1
416/17
FREF
1 16
CRYSTAL CHARGE PUMP DRIVE
LOCK DET CHARGE PUMP
PE 1-BIT COUNT 17-BIT LATCH DIVIDE RATIO
C1, C0 2-BIT LATCH 2-BIT LATCH
MODE CONTROL
DISABLE
5-BIT LATCH AND MODE CONTROL LOGIC (SEE TABLE 6) ADDRESS SDA SCL ADC
4 5 6 11
FPD/2 I 2C TRANSCEIVER 3-BIT ADC
3
FL 4-BIT LATCH AND PORT INTERFACE
P0 TEST CONTROL
12 15
VCC VEE
POWER ON DETECT
7 8 9 10
P3
P2
P1
P0
Figure 2 - Block diagram
3
SP5659
Preliminary Information
respectively. After two complete data bytes have been received, additional data bytes can be entered, where byte interpretation follows the same procedure without readdressing the device. This procedure continues until a STOP condition is received. The STOP condition can be generated after any data byte; if, however, it occurs during a byte transmission then the previous data is retained. To facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 17 bits of the data have been received or after the generation of a STOP condition. Repeatedly sending bytes 2 and 3 only will not change the frequency. A frequency change when one of the following data sequences is sent to an addressed device: Bytes 2, 3, 4, 5 Bytes 4, 5, 2, 3 or when a STOP condition follows valid data bytes thus: Bytes 2, 3, 4, STOP Bytes 4, 5, 2, STOP Bytes 2, 3, STOP Bytes 2, STOP Bytes 4, STOP It should be noted that the SP5569 must be addressed initially with both frequency AND control byte data, since the control byte contains reference divider information which must be provided before a chosen frequency can be synthesised. This implies that after initial turn on, bytes 2, 3 and 4 must be sent followed by a STOP condition as a minimum requirement. Alternatively, bytes 2, 3, 4 and 5 must be sent if port information is also required.
FUNCTIONAL DESCRIPTION
The SP5659 contains all the elements necessary - with the exception of a frequency reference, loop filter and external high voltage transistor - to control a varactor tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic which enables the generation of a loop with good phase noise performance. The block diagram is shown in Fig. 2. The RF input signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier interfaces with a 17-bit fully programmable divider via a 42 prescaler. For applications up to 2*0GHz RF input, the prescaler can be disabled, so eliminating the degradation in phase noise due to prescaler action. The divider is of MN1A architecture, where N = 16 or 17, the M counter is 13 bits and the A counter is 4 bits. The output of the programmable divider, FPD, is fed to the phase comparator where it is compared in phase and frequency domains with the comparison frequency FCOMP. This frequency is derived either from the on-chip crystal controlled oscillator or from an external reference source. In either case, the reference frequency FREF is divided down to the comparison frequency by the reference divider, which is programmable to one of 15 ratios as detailed in Table 1. The output of the phase detector feeds a charge pump and loop amplifier section which, when used with an external high voltage transistor and loop filter, integrates the current pulses into the varactor line voltage. By invoking the device test modes as described in Fig. 3, Table 6, the varactor drive output can be disabled, so switching the external transistor off. This allows an external voltage to be applied to the varactor line for tuner alignment purposes. Similarly, the charge can also be disabled to a high impedance state. The programmable divider output FPD/2 can be switched to port P0 by programming the device into test mode as set out in Table 6.
READ Mode
When the device is in read mode the status byte read from the device on the SDA line takes the form shown in Fig. 3, Table 3. Bit 1 (POR) is the power-on reset indicator and is set to a logic `1' if the VCC supply to the device has dropped below 3V (at 25C), for example, when the device is initially turned on. The POR is reset to 0 when the read sequence is R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Ratio 2 4 8 16 32 64 128 256 Invalid 5 10 20 40 80 160 320 800kHz 400kHz 200kHz 100kHz 50kHz 25kHz 12*5kHz Comparison frequency 2MHz 1MHz 500kHz 250kHz 125kHz 62*5kHz 31*25kHz 15*625kHz
PROGRAMMING
The SP5659 is controlled by an I2C Bus. Data and Clock are fed in on the SDA and SCL lines respectively, as defined by the I2C Bus format. The synthesiser can either accept new data (write mode) or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low and read mode if it is high. Tables 1 and 2 in Fig. 3 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an I2C Bus system. Table 4 in Fig. 3 shows how the address is selected by applying a voltage to the address input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during following acknowledge periods after further data bytes are programmed. When the device is programmed into the read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal STOP condition, which inhibits further reading.
WRITE Mode (Frequency Synthesis)
With reference to Table 2, bytes 2 and 3 contain frequency information bits 214 to 20 inclusive. Auxiliary frequency bits 216 and 215 are in byte 4. For most frequencies, only bytes 2 and 3 will be required. The remainder of byte 4 and byte 5 control the prescaler enable, reference divider ratio (see Fig. 3), output ports and test modes (see Table 6). After reception and acknowledgment of a valid address (byte 1), the first bit of the following byte determines whether the byte is interpreted as byte 2 (logic `0') or byte 4 (logic `1'); the next data byte is then interpreted as byte 3 or byte 5,
Table 1 - Reference division ratios (4MHz external reference)
4
Preliminary Information
terminated by a STOP command. When POR is set high (at low VCC), the programmed information is lost and the output ports are all set to high impedance. Bit 2 (FL) indicates whether the device is phase locked, a logic `1' is present if the device is locked, and a logic `0' if the device is unlocked. Bits 6, 7 and 8 (A2, A1, A0) combine to give the output of the ADC. The ADC can be used to feed AFC information to the microprocessor via the I 2C bus.
SP5659
Additional Programmable Features
Prescaler enable The 42 prescaler is enabled by setting bit PE in byte 4 to a logic `1'. A logic `0' disables the prescaler, directly passing the RF input to the 17-bit counter. Bit PE is a static select only. Charge pump current The charge pump current can be programmed by bits C1 and C0 in data byte 5, as defined in Fig. 3, Table 7. MSB Address 1
7
Test mode The test modes are invoked by setting bit RE to logic `0' and bit RTS to logic `1' within the programming data and are selected by bits TS2, TS1 and TS0 as shown in Fig. 3, Table 6. When TS2, TS1 and TS0 are received, the device retains previously P2, P1 and P0 data. Reference comparison frequency output The reference frequency FREF can be switched to the REF/ COMP output (pin 3) by setting byte 5 bit RE to logic `1' and bit RTS to logic `0'. The comparison frequency FCOMP can be switched to the REF/COMP output by setting bit RE to logic `1' and bit RTS to logic `1'. For RE set to logic `0', the output is disabled and set to a high state. RE and RTS default to logic `1' during power-up, thus enabling FCOMP at the REF/COMP output.
LSB 1 2
14 6
0 2
13 5
0 2
12 4
0 2
11 3
MA1 2
10 2
MA0 2 2
9 1
0 2 2
8 0
A A A A A
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5
Programmable divider 0 Programmable divider 2 Control data Control data 1 C1
2
2
2
2
2
216 C0
215
PE
R3
R2
R1
R0
RE RTS
P3 P2/TS2 P1/TS1 P0/TS0
Table 1 Write data format (MSB transmitted first)
Address Status byte 1 1 0 X 0 X 0 X MA1 MA0 A2 A1 1 A0 A A Byte 1 Byte 2
POR FL
Table 3 Read data format
A2 1 0 0 0 0 A1 0 1 1 0 0 A0 0 1 0 1 0 Voltage on ADC input 0*6V CC to VCC 0*45VCC to 0*6VCC 0*3VCC to 0*45VCC 0*15VCC to 0*3VCC 0V to 0*15VCC MA1 MA0 0 0 1 1 0 1 0 1 Address input voltage level 0V to 0*1VCC Open circuit 0*4VCC to 0*6VCC 0*9VCC to VCC
Table 4 ADC levels
A MA1, MA0 216-2 0 PE R3, R2, R1, R0 C1, C0 RE RTS TS2, TS1, TS0 P0 P3, P2, P1 POR FL A2, A1, A0 X : : : : : : : : : : : : : : :
Table 5 Address selection
Acknowledge bit Variable address bits (see Table 5) Programmable division ratio control bits Prescaler enable Reference division ratio select (see Table 1) Charge pump current select (see Table 7) Reference oscillator output enable REF/COMP select when RE = 1, Test mode enable when RE = 0 (see Table 6) Test mode control bits (valid when RE = 0 and RTS = 1,see Table 6) Port P0 output state (always valid except when RE = 0 and RTS = 1 (see Table 6) Ports P2, P1 and P0 output states Power on reset indicator Phase lock flag ADC data (see Table 4) Don't care Figure 3 - Data formats cont...
5
SP5659
Preliminary Information
RE RTS TS2 TS1 TS0 REF/COMP O/P mode 0 0 0 0 0 0 1 1 0 1 1 1 1 1 0 1 X X X X X 1 X X X 0 0 1 1 X X X X 0 1 0 1 X X X Disabled to high state Disabled to high state Disabled to high state Disabled to high state Disabled to high state FREF switched F COMP switched
Test mode description Normal operation Charge pump sink, status byte FL = 1 Charge pump source, status byte FL = 0 Port P0 = FPD/2 Varactor drive output disabled Normal operation Normal operation
Disabled to high state Charge pump disabled, status byte FL = 0
Table 6 - REF/COMP output mode and test modes
C1 0 0 1 1
C0 Min. +- 9 0 +-195 +-416 +-900 0 1 0 1
A) Current (
Typ. +-1 2 0 +-2 6 0 +-5 5 5 + - 1200 Max. +-150 +-325 +-694 +-1500
byte 5, bit 1 byte 5, bit 2
Table 7 - Charge pump current Figure 3 - Data formats (continued)
300
300
VIN (mV RMS INTO 50 )
100
VIN (mV RMS INTO 50 )
100
OPERATING WINDOW
OPERATING WINDOW
40
40
10 100 1000 2000 3000 3500
10 100 300 1000 2000 2700 3000 3500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4a - Prescaler disabled, PE = 0
Figure 4b - Prescaler enabled, PE = 1
Figure 4 - Typical input sensitivity
6
Preliminary Information
DOUBLE CONVERSION TUNER SYSTEMS
The high 2*7GHz maximum operating frequency and excellent noise characteristics of the SP5659 allow the construction of double conversion high IF tuners. A typical as shown in Fig. 5 uses the SP5659 as the first local oscillator control for full band up conversion to an IF of greater
SP5659
than 1GHz. The wide range of reference division ratios allows the SP5659 to be used for both the up converter local oscillator with a high phase comparison frequency (hence low phase noise) and the down converter which uses the device in a lower comparison frequency mode, which gives a fine step size.
1*6GHz 50-900MHz 38*9MHz
1650-2700MHz REFERENCE CLOCK FIRST LO SP8659 SECOND LO SP8659
Figure 5 - Example of double conversion from VHF/UHF frequencies to TV IF
4MHz 18p
1 2 SP5659 3
130V 112V 16k 13*3k
1 2 16 15 14 13
68p 15n
22k 47k 2*2n
Optional application using on-chip crystal controlled oscillator
REF 10n
BCW31
TUNER
1n 1n OSCILLATOR OUTPUT 15V ADC P0 P1 10n
REF/COMP
3 4
CONTROL MICRO
ADDRESS SDA SCL P3 P2
SP5659
5 6 7 8 12 11 10 9
Figure 6 - Typical application
APPLICATION NOTES
An application note, AN168, is available for designing with synthesisers such as the SP5659. It covers aspects such as loop filter design and decoupling. The application note is published in the Zarlink Semiconductor Media IC Handbook. A generic test/demonstration board has been produced, which can be used for the SP5659. A circuit diagram and layout for the board are shown in Figs. 7 and 8. The board can be used for the following purposes: (A) Measuring RF sensitivity performance (B) Indicating port function (C) Synthesising a voltage controlled oscillator (D) Testing external reference sources The programming codes relevant to these tests are given in Fig. 3.
7
SP5659
Preliminary Information
EXTERNAL REFERENCE SK2 C7 100n C3 68p C2 15n R6 13*3k X1 4MHz P1 DISABLE/REF ENABLE DATA/SDA CLOCK/SCL C13 100p C14 100p C1 18p
1 2 3 4 5 6 7 8 16 15 14 13 12
15V P2 C8 100n
130V
112V
C9 100n
C6 10n (NOT FITTED, SEE NOTE 3)
R8 22k R8 16k TR1 2N3904 R9 47k C12 2*2n C5 1n C4 1n SK1 RFINPUT 15V C10 1n
11 10 9
P3 VAR GND
NOTES 1. The circuit diagram shown is designed for use with a number of synthesisers. P4 2. The LED connected to pin 11 is redundant when an SP5659 is used in this board. 3. To use an external reference, D1 capacitor C6 must be fitted and capacitor C1 removed from the board.
R1 4*7k
R2 4*7k
R3 4*7k
R4 4*7k
R5 4*7k
D2
D3
D4
D5
112V C11 1n
Figure 7 - Test board circuit diagram
RJM51 BOTTOM SILK SCREEN COMPONENT LOCATION Figure 8 - Test board layout
8
Preliminary Information
LOOP BANDWIDTH
Most applications for which the SP5659 is intended require a loop filter bandwidth of between 2kHz and 10kHz. Typically, the VCO phase noise will be specified at both 1kHz and 10kHz offset. It is common practice to arrange the loop filter bandwidth such that the 1kHz figure lies within the loop bandwidth. The phase noise therefore depends on the synthesiser comparator noise floor rather than the VCO The 10kHz offset figure should depend on the VCO provided that the loop has been designed correctly and is not underdamped.
SP5659
Assuming the phase comparator noise floor is flat regardless of sampling frequency, this means that the best performance will be achieved when the overall local oscillator to phase comparator division ratio is a minimum. The are two ways of achieving a higher phase comparator sampling frequency: 1. Reduce the division ratio between the reference source and the phase comparator 2. Use a higher reference source frequency The second approach may be preferred for best performance since it is possible that the noise floor of the reference oscillator may degrade the phase comparator performance if the reference division ratio is very small.
REFERENCE SOURCE
The SP5659 offers optimal local oscillator phase noise performance when operated with a large step size. This is because the local oscillator phase noise within the loop bandwidth is: FLO Phase comparator noise floor 120log10 FCOMP where F LO is the local oscillator frequency and FCOMP is the phase comparator frequency.
DRIVING TWO SP5659s FROM A COMMON REFERENCE
The REF/COMP output on pin 3 allows two synthesisers to be driven from a common reference. To do this, the first device should be programmed by setting RE = 1 and RTS = 0. The driven device should be programmed for normal operation with RE = 0 and RTS = 0. The two devices should be connected as shown in Fig. 9.
4MHz 18p
1 2 3 4
16 15 14 13
1n
1 2 3 4
16 15 14 13
SP5659
5 6 7 8 12 11 10 9 5 6 7 8
SP5659
12 11 10 9
Figure 9 - Two SP5659 devices using a common reference
j1 j 0.5 j2
j 0.2 j5
0
0.2
0.5
1
2
5
2j 5 2j 0.2
S11:ZO = 50 NORMALISED TO 50
2j 0.5 2j 1
2j 2
FREQUENCY MARKERS AT 100MHz, 500MHz, 1GHz AND 2*7GHz
Figure 10 - Typical RF input impedance
9
SP5659
Preliminary Information
VCC
VREF
1
CHARGE PUMP
500
13
500
RF INPUT RF INPUT
14
200 100 OS (O/P DISABLE)
16
DRIVE OUTPUT
RF inputs
Loop amplifier
VCC
VCC
30k 3k 3k SCL/SDA/ADC ADDRESS
4
10k
*
ACK
* ON SDA ONLY
SDA, SCL and ADC Address input
VCC VCC PORT
3
REF/COMP ENABLE/ DISABLE CRYSTAL
2
Reference oscillator
Output ports
REF/COMP output
Figure 11 - Input/output interface circuits
10
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Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001, Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
For more information about all Zarlink products visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002, Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE

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